HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 53

• Manufacturer Part Number: HYB18M1G320BF
• Description: DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1) All parameters assume proper device initialization.
2) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for
3) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
4) The output timing reference level is
5) Parameters
6) Min (
7)
8) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
9) DQ, DM and DQS input slew rate is measured between
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16)
17)
18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
19) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Parameter
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
AUTO REFRESH to ACTIVE/AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
WRITE recovery time
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
CKE minimum high or low time
Refresh period
Average periodic refresh interval (8192 rows)
signals other than CK/CK is V
a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half
drive strength with a nominal load of 10pF parameters
are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation
is suggested.
be greater than the minimum specification limits for
t
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
through the DC region must be monotonic.
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
t
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t
performance (bus turnaround) will degrade accordingly.
QH
HZ
DQSQ
and
=
t
t
CL
consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
HP
,
t
LZ
t
-
CH
t
QHS
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
t
AC
, where
and
t
DQSCK
t
HP
= minimum half clock period for any given cycle and is defined by clock high or clock low (
are specified for full drive strength and a reference load (see
DDQ
/2.
V
DDQ
/2.
DQSS
.
t
CL
t
and
AC
V
ILD(DC)
and
t
CH
).
t
DQSCK
and
53
V
are expected to be in the same range. However, these parameters
IHD(AC)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RAS
RC
RFC
RCD
RP
RRD
WR
DAL
WTR
XSR
XP
CKE
REF
REFI
V
(rising) or
IH
and
V
45
65
75
22.5
22.5
15
15
1
120
t
2
–
–
IL
CK
.
V
Figure 39
min.
+
IHD(DC)
t
IS
- 7.5
and
). This circuit is not intended to be either
70,000
–
–
–
–
–
–
–
–
–
–
64
7.8
V
max.
ILD(AC)
1-Gbit DDR Mobile-RAM
(falling).
HY[B/E]18M1G320BF
Unit
ns
ns
ns
ns
ns
ns
ns
t
t
ns
ns
t
ms
µs
CK
CK
CK
t
CL
,
t
CH
Note
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)22)
1)2)3)
1)2)3)21)
1)2)3)
1)2)3)
1)2)3)
1)2)3)23)
).
Data Sheet
t
QHS
accounts