HYB18L256169BF QIMONDA [Qimonda AG], HYB18L256169BF Datasheet
HYB18L256169BF
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HYB18L256169BF Summary of contents
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... HYB18L256169BF-7.5, HYE18L256169BF-7.5 Revision History: 2006-12, Rev.1.02 Page Subjects (major changes since last revision) All Qimonda update Previous Version: 2005-05, Rev. 1.01 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... ACmax t Clock Cycle Time ( ) CKmin Table 2 Memory Addressing Scheme Item Banks Rows Columns 1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers ...
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... Ordering Information 1) Type Package Commercial Temperature Range 133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM HYB18L256169BF-7.5 Extended Temperature Range 133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM HYE18L256169BF-7.5 1) HY[B/E]: Designator for memory products (HYB: standard temp. range); (HYE: extended temp. range) 18L: 1.8V Mobile-RAM 256: 256 MBit density ...
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... Description The HY[B/E]18L256169BF is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. The HY[B/E]18L256169BF achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented ...
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... SELF REFRESH. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple memory banks considered part of the command code. RAS, CAS, Input Command Inputs: RAS, CAS and WE (along with CS) define the command being WE entered ...
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... Functional Description The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...
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At first, device core power (V ) and device IO power (V DD and V are driven from a single power converter output. DDQ Assert and hold CKE and DQM to a HIGH level. 2. After V and V ...
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Field Bits Type Description BL [2:0] w Burst Length 000 1 001 2 010 4 011 8 111 full page (Sequential burst type only) Note: All other bit combinations are RESERVED. 2.2.1.1 Burst Length READ and WRITE accesses to the ...
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Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 2.2.1.2 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred ...
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... Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks, two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a t period defined by (cf ...
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State Diagram Figure 4 State Diagram Data Sheet HY[B/E]18L256169BF-7.5 256-Mbit Mobile-RAM Functional Description 12 02032006-MP0M-7FQG Rev. 1.02, 2006-12 ...
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... DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are placed in High-Z state (two clocks latency) during read cycles. ...
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Table 7 Inputs Timing Parameters Parameter Clock cycle time Clock frequency Clock high-level width Clock low-level width Address and command input setup time Address and command input hold time 2.4.1 NO OPERATION (NOP) Figure 6 No Operation Command 2.4.2 DESELECT ...
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MODE REGISTER SET Figure 7 Mode Register Set Command Figure 8 Mode Register Definition Table 8 Timing Parameters for Mode Register Set Command Parameter MODE REGISTER SET command period Data Sheet HY[B/E]18L256169BF-7.5 256-Mbit Mobile-RAM The Mode Register and Extended ...
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ACTIVE Figure 9 ACTIVE Command Figure 10 Bank Activate Timings Table 9 Timing Parameters for ACTIVE Command Parameter ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay 1) These ...
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READ Figure 11 READ Command Figure 12 Basic READ Timing Parameters for DQs Data Sheet HY[B/E]18L256169BF-7.5 256-Mbit Mobile-RAM Functional Description Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with a READ ...
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Table 10 Timing Parameters for READ Parameter Access time from CLK DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) ACTIVE to ACTIVE command period ACTIVE to READ ...
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Figure 14 Single READ Burst (CAS Latency = 3) Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. A READ command can be ...
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Figure 16 Random READ Bursts Non-consecutive READ bursts are shown in Figure 17 Non-Consecutive READ Bursts Data Sheet Figure 17. 20 HY[B/E]18L256169BF-7.5 256-Mbit Mobile-RAM Functional Description Rev. 1.02, 2006-12 02032006-MP0M-7FQG ...
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READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command must ...
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READ - DQM Operation DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing parameters as listed in Table 10 also apply to this DQM operation. The read burst in ...
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READ to PRECHARGE A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued x clock ...
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WRITE Figure 23 WRITE Command Figure 24 Basic WRITE Timing Parameters for DQs During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and subsequent data elements are registered on each successive positive edge ...
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Table 11 Timing Parameters for WRITE Parameter DQ and DQM input setup time DQ input hold time DQM input hold time DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command ...
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Figure 26 WRITE Burst (CAS Latency = 3) Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. A WRITE command can ...
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Figure 28 Random WRITE Bursts Non-consecutive WRITE bursts are shown in Figure 29 Non-Consecutive WRITE Bursts 2.4.6.1 WRITE Burst Termination Data from any WRITE burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. ...
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Figure 30 Terminating a WRITE Burst 2.4.6.2 Clock Suspend Mode for WRITE Cycles Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following ...
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WRITE - DQM Operation DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The generic timing parameters as listed in in progress is not affected and ...
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WRITE to PRECHARGE A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued the WRITE ...
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PRECHARGE Figure 36 PRECHARGE Command 2.4.8.1 AUTO PRECHARGE Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in ...
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CONCURRENT AUTO PRECHARGE A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE command issued to a different bank. Figure 37 shows a READ with Auto Precharge to bank n, interrupted ...
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Figure 39 WRITE with Auto Precharge Interrupted by READ Figure 40 WRITE with Auto Precharge Interrupted by WRITE Data Sheet HY[B/E]18L256169BF-7.5 256-Mbit Mobile-RAM Functional Description 33 02032006-MP0M-7FQG Rev. 1.02, 2006-12 ...
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AUTO REFRESH and SELF REFRESH The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event in ...
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SELF REFRESH Figure 43 SELF REFRESH Entry Command Figure 44 Self Refresh Entry and Exit Table 13 Timing Parameters for AUTO REFRESH and SELF REFRESH Parameter ACTIVE to ACTIVE command period PRECHARGE command period Refresh period (8192 rows) Self ...
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... The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this mode. To enter the deep power down mode all banks must be precharged. ...
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Function Truth Tables Table 14 Current State Bank n - Command to Bank n Current State CS RAS CAS WE Command / Action Any Idle ...
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The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when SDRAM ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not ...
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Electrical Characteristics 3.1 Operating Conditions Table 17 Absolute Maximum Ratings Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those ...
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Table 19 Electrical Characteristics Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage I Output high voltage ( = -0.1 mA Output low voltage ( = 0.1 mA) OL Input ...
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AC Characteristics 1)2)3)4) Table 20 AC Characteristics Parameter Clock cycle time Clock frequency Access time from CLK Clock high-level width Clock low-level width Address, data and command input setup time Address and command input hold time Data (DQ) input ...
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Operating Currents Table 21 Maximum Operating Currents Parameter & Test Conditions Operating current: one bank: t active / read / precharge Precharge power-down standby current: all banks idle, CS ≥ , CKE ≤ ...
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Table 22 Self Refresh Currents Parameter & Test Conditions Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter ...
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Package OutlinesPG-VFBGA-54-8 (Plastic Green Very Thin Fine Pitch Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Qimonda Internet Page : http://www.qimonda.com/products. SMD = Surface Mounted Device Data Sheet HY[B/E]18L256169BF-7.5 256-Mbit ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2006-12 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ...