HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 31

• Manufacturer Part Number: HYB18M1G320BF
• Description: DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1) DQ, DM and DQS input slew rate is measured between
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
3) Input slew rate ≥ 1.0 V/ns.
4) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
8)
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command,
and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is
known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (
is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in
of
High-Z and any additional input data is ignored.
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Parameter
Write postamble
Write preamble
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
WRITE recovery time
Internal write to Read command delay
PRECHARGE command period
t
DQSS
through the DC region must be monotonic.
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t
performance (bus turnaround) will degrade accordingly.
These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain
DQSS
.
V
ILD(DC)
and
31
V
IHD(AC)
(rising) or
t
t
t
t
t
t
t
t
WPST
WPRE
RAS
RC
RCD
WR
WTR
RP
Symbol
V
IHD(DC)
and
0.4
0.25
45
65
22.5
15
1
22.5
min.
V
Figure 23
ILD(AC)
- 7.5
1-Gbit DDR Mobile-RAM
(falling).
0.6
–
70,000
–
–
–
–
–
HY[B/E]18M1G320BF
max.
show the two extremes
Unit
t
t
ns
ns
ns
ns
t
ns
CK
CK
CK
Data Sheet
Note
7)
–
8)
8)
8)
8)
–
8)
t
DQSS
)