NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 32

• Manufacturer Part Number: NAND08GW3C2B
• Description: 8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

6 Device operations
6.12
6.13
32/60
Reset
The Reset command resetd the command interface and Status Register. If the Reset
command is issued during any operation, the operation is aborted. If it is a program or erase
operation that is being aborted, the contents of the memory locations being modified are no
longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for t
of t
issued. Refer to
Read Status Register
The device contains a Status Register that provides information on the current or previous
program or erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable, or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
Status Register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read operation.
Refer to
with the following text descriptions.
Table 9.
I/O
0
1
2
3
4
5
6
7
BLBH4
Table 9
Plane 0: Pass/fail
Plane 1: Pass/fail
depends on the operation that the device was performing when the command was
Page program
Write protect
Ready/busy
Status Register bits
(SP/DP)
Pass/fail
NA
NA
NA
Table 23
which summarizes Status Register bits and should be read in conjunction
for the values.
Plane 0 Pass/fail
Plane 1 Pass/fail
Write protect
Block erase
Ready/busy
(SD/DP)
Pass/fail
NA
NA
NA
BLBH4
after the Reset command is issued. The value
Write protect Protected: ‘0’, Not protected: ‘1’
Ready/busy
Page read
NAND08GW3C2B, NAND16GW3C4B
NA
NA
NA
NA
NA
NA
Pass: ‘0’, Fail: ‘1’
Plane 0: Pass: ‘0’, Fail: ‘1’
Plane 1: Pass: ‘0’, Fail: ‘1’
-
-
-
Busy: ‘0’, Ready: ‘1’
Definition