NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 29

• Manufacturer Part Number: NAND08GW3C2B
• Description: 8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GW3C2B, NAND16GW3C4B
6.9
Multiplane page program
The devices support multiplane page program, that allows the programming of two pages in
parallel, one in each plane.
A multiplane page program operation requires two steps:
1.
2.
As for standard page program operations, the device supports random data input during
both data loading phases.
Once the multiplane page program operation has started, maintaining a delay of t
Status Register can be read using the Read Status Register command. Once the multiplane
page program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the Status Register.
However, there is no way to identify for which page the program operation failed.
The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
–
–
–
The second step programs, in parallel, the two pages of data loaded into the data buffer
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
One clock cycle to set up the Page Program command (see
Sequential
Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0).
One bus write cycle to issue the Page Program Confirm code. After this the device
is busy for a time of t
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the second page address (5 write
cycles) and data. The address of the second page must be within the second
plane (A19=1), and A18 to A12 must be the address bits loaded during the first
address insertion.
input).
BLBH5
.
Section 6.5:
6 Device operations
BLBH5
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, the