NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 15

no-image

NAND08GW3C2B

Manufacturer Part Number
NAND08GW3C2B
Description
8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NAND08GW3C2BN6E
Manufacturer:
ST
0
NAND08GW3C2B, NAND16GW3C4B
3
3.1
3.2
3.3
3.4
3.5
3.6
Signal descriptions
See
signals connected to this device.
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation, or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
High, v
mode.
E
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid t
column address counter by one.
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
2
is only available on the NAND16GW3C4B.
Figure 1: Logic block
RLQV
IH
, while the device is busy, the device remains selected and does not go into standby
after the falling edge of R. The falling edge of R also increments the internal
1
, E
diagram, and
2
)
Table 2: Signal names
IL
, the device is selected. If Chip Enable goes
for a brief overview of the
3 Signal descriptions
15/60

Related parts for NAND08GW3C2B