NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 30

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NAND08GW3C2B

Manufacturer Part Number
NAND08GW3C2B
Description
8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet

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6 Device operations
Figure 14. Multiplane page program
1. Note that the same addresses except for A19 apply to both blocks.
2. No command between 11h and 81h is permitted except 70h and FFh.
6.10
30/60
RB
I/O
Page Program
Setup Code
80h
Input
Data
A12-A18: Fixed 'Low'
A20-A30: Fixed 'Low'
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The erase operation is initiated on the rising edge of Write Enable, W, after the Confirm
command is issued. The P/E/R Controller handles block erase and implements the verify
process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Address Inputs
A19: Fixed 'Low'
A0-A11: Valid
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A31 are used; the other address inputs are ignored.
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
80h
Table 6
Data Input
for the block addresses of each device.
(2048 blocks)
Block 4092
Block 4094
Block 0
Block 2
Plane 0
. .
tBLBH5
Confirm
Code
11h
Busy
Multiplane Page
Program Setup
11h
Code
81h
Address Inputs
A19: Fixed 'High'
A12-A18: Valid
A20-A30: Valid
81h
A0-A11: Valid
Figure
NAND08GW3C2B, NAND16GW3C4B
(2048 blocks)
Block 4093
Block 4095
Data Input
Block 1
Block 3
Plane 1
15):
. .
(Program Busy time)
tBLBH2
Confirm
Code
10h
Busy
10h
Read Status Register
70h
ai13636b
SR0

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