NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 26

• Manufacturer Part Number: NAND08GW3C2B
• Description: 8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

6 Device operations
Figure 10. Random data input during sequential data input
6.7
26/60
RB
I/O
Row Add 1,2,3
Code
Cmd
80h
Copy-back program
The copy-back program with read for copy-back operation is configured to quickly and
efficiently rewrite data stored in one page without data reloading when the bit error is not in
data stored.
Since the time-consuming re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest
of the block also needs to be copied to the newly-assigned free block. The copy-back
operation is a sequential execution of read for copy-back and copy-back program with the
destination page address. A read operation with a 35h command in the address of the
source page moves the entire 2112 bytes into the internal data buffer. A bit error is checked
by sequentially reading the data output. In the case where there is no bit error, the data does
not need to be reloaded. Therefore, the copy-back program operation is initiated by issuing
the Page-Copy Data-Input command (85h) with destination page address.
The actual programming operation begins after the Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be
entered to read the Status Register. The system controller can detect the completion of a
program cycle by monitoring the RB#output, or the status bit (I/O 6) of the Status Register.
When the copy-back program is complete, the write status bit (I/O 0) may be checked. The
Command Register remains in read status command mode until another valid command is
written to the command register. During the copy-back program, data modification is
possible using random data input command (85h) as shown in
5 Add cycles
Address
Inputs
Col Add 1,2
Main Area
Data Intput
Spare
Code
Area
Cmd
85h
2 Add cycles
Address
Col Add 1,2
Inputs
Data Input
(Program Busy time)
NAND08GW3C2B, NAND16GW3C4B
tBLBH2
Confirm
Code
10h
Main Area
Figure
Busy
Read Status Register
11.
70h
Spare
Area
SR0
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