NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet
NAND08GW3C2B
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NAND08GW3C2B Summary of contents
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... Multiblock erase time (2 blocks): 2.5 ms (typ) ■ Status register ■ Electronic signature March 2008 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. NAND08GW3C2B NAND16GW3C4B Gbit, 2112 byte page, TSOP48 (N) LGA52 (N) ■ Serial number option ■ ...
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... Write Protect (WP 3.8 Ready/Busy (RB 3.9 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DD 3.10 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/60 NAND08GW3C2B, NAND16GW3C4B , ...
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... NAND08GW3C2B, NAND16GW3C4B 6.5 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 Random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 Copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8 Multiplane copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.11 Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.12 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.13 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.13.1 6.13.2 6.13.3 6.14 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Concurrent operations and ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 ...
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... Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4/60 NAND08GW3C2B, NAND16GW3C4B ...
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... NAND08GW3C2B, NAND16GW3C4B List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Valid blocks Table 4. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Paired page address information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Status Register bits Table 10. Device identifier codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 11. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 12. ...
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... List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TSOP48 connections for NAND08GW3C2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. TSOP48 connections for NAND16GW3C4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. ULGA52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11 ...
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... Read operation. There is the option of a unique identifier (serial number), which allows the NAND08GW3C2B and the NAND16GW3C4B to be uniquely identified subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx sales office. ...
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... K 3.6 V 128 bytes pages x 8192 blocks P/E/R controller high voltage generator NAND08GW3C2B, NAND16GW3C4B Timings Random Sequential Page Block access access program erase time time (min) (typ) (typ) (max µs 800 µs NAND Flash ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 2. Logic diagram 1. E2 and RB2 are only present in the NAND16GW3C4A. Table 2. Signal names Signal I/ the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of I/Os and control signals ...
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... Description Figure 3. TSOP48 connections for NAND08GW3C2B 10/60 NAND08GW3C2B, NAND16GW3C4B NAND Flash I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI13633 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 4. TSOP48 connections for NAND16GW3C4B RB2 RB1 NAND FLASH Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI13169 11/60 ...
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... On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of signals. 12/ I/ I/O1 1 I/O6 1 I/O2 1 I/ I/O4 2 I/O3 2 NAND08GW3C2B, NAND16GW3C4B ...
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... Figure 6: Memory array 2.1 Bad blocks The NAND08GW3C2B and NAND16GW3C4B devices may contain bad blocks, where the reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block Information is written prior to shipping (refer to management for more details) ...
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... Page Buffer, 2112 Bytes 2,048 Bytes 14/60 x8 bus width Plane = 2048 blocks Block = 128 Pages Page = 2112 Bytes (2,048 + 64) Second Plane Main Area 2048 Bytes 64 Bytes Bytes Page Buffer, 2112 Bytes 64 2,048 Bytes Bytes Bytes 2 Page Buffer, 2x 2112 Bytes NAND08GW3C2B, NAND16GW3C4B 8 bits bits AI13170 ...
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... NAND08GW3C2B, NAND16GW3C4B 3 Signal descriptions See Figure 1: Logic block signals connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs are used to input the selected address, output the data during a read operation, or input a command or data during a write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled ...
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... DD power supply for operations (read, program and erase). 3.10 V ground SS Ground the reference for the power supply. It must be connected to the system SS, ground. 16/60 NAND08GW3C2B, NAND16GW3C4B , read, program or erase operation is in progress. When the the device does not accept IL , during power-up and power-down. ...
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... NAND08GW3C2B, NAND16GW3C4B 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section. See the summary in Typically, glitches of less than Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. ...
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... Bus operations Bus operation Command input Address input Data input Data output Write protect Standby 1. WP must be V when issuing a program or erase command. IH 18/60 NAND08GW3C2B, NAND16GW3C4B lower than 30 ns), the extended data out (EDO) mode must be RLRL Figure 24 ...
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... NAND08GW3C2B, NAND16GW3C4B Table 5. Address insertion Bus cycle I/ A19 th 4 A27 Any additional address input cycles are ignored. 2. A31 is valid only for the NAND16GW3C4B. Table 6. Address definitions Address A0 - A11 A12 - A18 A19 - A31 (1) I/O6 I/O5 I/O4 I/ ...
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... Multiplane Block Erase Read Status Register Random Data Input Random Data Output 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 20/60 NAND08GW3C2B, NAND16GW3C4B Table 7: Commands. Bus write operations ...
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... NAND08GW3C2B, NAND16GW3C4B 6 Device operations This section gives the details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, see subsequent consecutive read commands only require the confirm command code (30h). ...
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... Device operations Figure 7. Read operations I/O Address Input 00h Command Code 1. Highest address depends on device density. 22/60 NAND08GW3C2B, NAND16GW3C4B tBLBH1 30h Data Output (sequentially) Command Busy Code Ai11016 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 8. Random data output tBLBH1 (Read Busy time Address 30h I/O 000h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 6.4 Page program The page program operation is the standard operation to program data to the memory array. ...
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... NAND08GW3C2B, NAND16GW3C4B Paired page address 04h 01h 08h 03h 0Ch 07h 10h 0Bh 14h 0Fh 18h 13h 1Ch 17h 20h 1Bh 24h 1Fh ...
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... NAND08GW3C2B, NAND16GW3C4B 6.5 Sequential input To input data sequentially the addresses must be sequential and remain in one block. For sequential input, each page program operation comprises five steps: 1. One bus cycle is required to set up the Page Program (sequential input) command (see Table 7). 2. Five bus cycles are then required to input the program address (refer to 3 ...
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... When the copy-back program is complete, the write status bit (I/O 0) may be checked. The Command Register remains in read status command mode until another valid command is written to the command register. During the copy-back program, data modification is possible using random data input command (85h) as shown in 26/60 NAND08GW3C2B, NAND16GW3C4B tBLBH2 (Program Busy time) Address 85h ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 11. Copy-back Program operation Source I/O 00h Add Inputs Read Code (Read Busy time) RB Figure 12. Copy-back Program operation with random data input Source 35h I/O 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB Target 35h 85h Add Inputs Copy Back ...
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... Second plane Source page (1): Read for copy back on first plane Target page (2): Read for copy back on second plane (2) (3) (3): Two-plane copy back program Main area Spare area NAND08GW3C2B, NAND16GW3C4B Copy back Read Status Register code 2 Add. 5 10h 11h 81h cycles Col. Add Row Add ...
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... NAND08GW3C2B, NAND16GW3C4B 6.9 Multiplane page program The devices support multiplane page program, that allows the programming of two pages in parallel, one in each plane. A multiplane page program operation requires two steps: 1. The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It requires: – ...
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... Code Program Setup A19: Fixed 'High' Code A20-A30: Valid 81h 11h Plane 0 (2048 blocks) Block 0 Block Block 4092 Block 4094 NAND08GW3C2B, NAND16GW3C4B tBLBH2 (Program Busy time) Busy Data Input 10h 70h Confirm Read Status Register Code 10h Plane 1 (2048 blocks) Block 1 Block 3 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 15. Block Erase operation RB I/O 60h Block Erase Setup Code 6.11 Multiplane block erase The multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. It consists of three steps (refer to 1. Eight bus cycles are required to set up the Block Erase command and load the addresses of the blocks to be erased ...
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... Status Register bits Page program I/O (SP/DP) 0 Pass/fail 1 Plane 0: Pass/fail 2 Plane 1: Pass/fail Ready/busy 7 Write protect 32/60 NAND08GW3C2B, NAND16GW3C4B after the Reset command is issued. The value BLBH4 for the values. Block erase Page read (SD/DP) Pass/fail NA Plane 0 Pass/fail NA Plane 1 Pass/fail Ready/busy Ready/busy Write protect Write protect Protected: ‘ ...
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... NAND08GW3C2B, NAND16GW3C4B 6.13.1 Write protection bit (SR7) The write protection bit can identify if the device is protected or not. If the write protection bit is set to ‘1’ the device is not protected and program or erase operations are allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed ...
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... Device operations Table 12. Electronic signature byte 3 I/O I/O1-I/O0 I/O3-I/O2 Number of simultaneously I/O5-I/O4 programmed pages Interleaved programming I/O6 between multiple devices I/O7 34/60 Definition Die/package Cell type Write cache NAND08GW3C2B, NAND16GW3C4B Value Description 2-level cell 0 1 4-level cell 1 0 8-level cell 1 1 16-level cell ...
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... NAND08GW3C2B, NAND16GW3C4B Table 13. Electronic signature byte 4 I/O I/O1-I/O0 (without spare area) Spare area size I/O2 (byte/512 byte) I/O7, I/O3 Serial access time I/O5-I/O4 (without spare area) I/O6 Table 14. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 - I/O2 I/O6 - I/O4 I/O7 Definition Page size Block size Organization Definition Reserved Plane number Plane size (without redundant area) Reserved 6 Device operations ...
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... Extended Read Status Register commands Command Read 1st die status Read 2nd die status 36/60 for the description of the Extended Read Status Register command Table 9. for the definition of the Status Register bits. Address range Address 0x7FFFFFFF 0x7FFFFFFF < Address 0xFFFFFFF NAND08GW3C2B, NAND16GW3C4B 1 bus write cycle F1h F2h ...
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... NAND08GW3C2B, NAND16GW3C4B 8 Data protection The device has hardware features to protect against spurious program and erase operations. An internal voltage detector disables all functions whenever V V threshold recommended to keep LKO In the V range from V DD Low ( guarantee hardware protection during power transitions, as shown in IL Figure 17 ...
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... Figure 18. 9.2 NAND Flash memory failure modes The NAND08GW3C2B and NAND16GW3C4B devices may contain bad blocks, where the reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad blocks may develop during the lifetime of the device. To implement a highly reliable system, all the possible failure modes must be considered: ● ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 18. Bad block management flowchart 9.3 Garbage collection When a data page needs to be modified faster to write to the first available page and mark the previous page as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations recommended to implement a garbage collection algorithm ...
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... These models provide information such as AC characteristics, rise/fall times, and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS. 40/60 NAND08GW3C2B, NAND16GW3C4B ...
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... Page program time Block erase time Program/erase cycles (per block (with ECC) Data retention Number of partial program cycles (NOP) within the same page (main array or spare arrary) 10 Program and erase times and endurance cycles NAND08GW3C2B, NAND16GW3C4B Min Typ 800 2.5 10,000 10 Unit ...
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... Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins. Maximum voltage may overshoot to V 42/60 Table 18: Absolute maximum ratings Parameter Temperature under bias Storage temperature Input or output voltage Supply voltage + 2 V for less than 20 ns during transitions on I/O pins. DD NAND08GW3C2B, NAND16GW3C4B Value Min Max – 50 125 – 65 150 – 0.6 4.6 – 0.6 4 ...
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... NAND08GW3C2B, NAND16GW3C4B 12 DC and AC parameters This section summarizes the operating and measurement conditions as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristics tables are derived from tests performed under the measurement conditions summarized in Table 19: Operating and AC measurement operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Test conditions t minimum Sequential RLRL read E IL, OUT Program - Erase - E=V , WP=0 E=V -0.2, DD WP=0 3 3.6 V OUT - - I = -400 µ 2 0 Parameter NAND08GW3C2B, NAND16GW3C4B Min Typ Max - ± ±10 2 +0.3 DD -0.3 - 0 2.5 Value AL setup time Min ...
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... NAND08GW3C2B, NAND16GW3C4B Table 23. AC characteristics for operations Alt. Symbol Symbol t Address Latch Low to Read Enable ALLRL1 ALLRL2 t t BHRL RR t BLBH1 t t Ready/Busy Low to Ready/Busy High BLBH2 PROG t t BLBH3 BERS t t BLBH4 RST t t BLBH5 CBSY t t CLLRL CLR ...
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... Setup time) tWLWL tWLWL tWLWH tWLWH tWHWL tWHWL tWHALL tWHALL tDVWH tDVWH tWHDX tWHDX (Data Hold time) Adrress cycle 2 NAND08GW3C2B, NAND16GW3C4B tWHCLL (CL Hold time) tWHEH (E Hold time) tWHALH (AL Hold time) tWHDX (Data Hold time) tWLWL tWLWL tWLWH tWLWH tWHWL tWHALL tDVWH ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 22. Data input latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. The last data input is the 2112th. Figure 23. Sequential data output after Read AC waveforms E R tRLQV (R Accesstime) I/O tBHRL Low Low High applicable for frequencies lower than 33 MHz (i.e. t ...
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... W is High lower than 30 ns). RLRL tCLLRL tWHCLL tWHEH tWLWH tWHRL tDZRL tDVWH tWHDX (Data Hold time) 70h or 7Bh NAND08GW3C2B, NAND16GW3C4B tEHQX tEHQZ Data Out Data Out tELQV tEHQZ tEHQX tRHQZ tRLQV tRHQX Status Register Output tRHQZ tRHQX (2) ai13175 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 26. Read electronic signature AC waveform I/O 90h Read Electronic Signature Command 1. Refer to Table 11 for the values of the manufacturer and device codes, and to information contained in Byte 3, Byte 4, and Byte 5. tALLRL1 tRLQV (Read ES Access time) 00h Byte1 Byte2 Man. Device ...
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... Command Address N Input Code 50/60 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N 30h N cycle 4 cycle 5 Busy from Address N to Last Byte or Word in Page NAND08GW3C2B, NAND16GW3C4B tEHQZ tRLRL tRHQZ (Read Cycle time) Data Data Data N+1 N+2 Last Data Output ai13638 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 28. Page program AC waveform CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 5 cycle 3 Address Input Data Input 12 DC and AC parameters tWLWL tWHBL tBLBH2 (Program Busy time) ...
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... RB Block Erase Block Address Input Setup Command Figure 30. Reset AC waveform I/O FFh RB 52/60 tBLBH3 tWHBL (Erase Busy time) Add. Add. D0h cycle 2 cycle 3 Confirm Block Erase Code tBLBH4 (Reset Busy time) NAND08GW3C2B, NAND16GW3C4B 70h SR0 Read Status Register ai08043 ai08038c ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 31. Program/erase enable waveform W tVHWH WP RB I/O Figure 32. Program/erase disable waveform W tVLWH WP High RB I/O 80h 80h 12 DC and AC parameters 10h ai12477 10h ai12478 53/60 ...
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... Ready/Busy can be calculated using the following equation: P – V DDmax V OLmax R P min = ------------------------------------------------------------- + min = -------------------------- - + 8mA . r ready busy DEVICE RB Open Drain Output V SS NAND08GW3C2B, NAND16GW3C4B AI07564B ibusy AI07563B P ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 35. Resistor value versus waveform timings for Ready/Busy signal 25° 3 3.3 290 1.65 189 1.1 96 4.2 4.2 4 ibusy 12 DC and AC parameters 381 0.825 4 55/60 ...
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... NAND08GW3C2B, NAND16GW3C4B ® TSOP-G Inches Typ Min 0.0039 0.0020 0.0394 0.0374 0.0087 0.0067 0.0039 0.4724 0.4685 0.7874 ...
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... NAND08GW3C2B, NAND16GW3C4B Figure 37. LGA52 mm pitch, package outline E E2 Table 25. LGA52 mm pitch, package mechanical data Symbol Typ 0.700 b2 1.000 D 12.000 D1 6.000 D2 10.000 ddd E 17.000 E1 12.000 E2 13.000 e 1.000 eE1 2.000 FD 3.000 FD1 1.000 FE 2.500 FE1 2.000 ...
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... F = ECOPACK® package, tape and reel packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ‘1’. For further information on any aspect of this device, please contact your nearest Numonyx sales office. 58/60 NAND08GW3C2B, NAND16GW3C4B NAND08G ...
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... NAND08GW3C2B, NAND16GW3C4B 15 Revision history Table 27. Document revision history Date 25-Feb-2008 19-Mar-2008 Revision 1 Initial release. 2 Applied Numonyx branding. 15 Revision history Changes 59/60 ...
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... Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 60/60 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. NAND08GW3C2B, NAND16GW3C4B ...