NAND08GW3C2B NUMONYX [Numonyx B.V], NAND08GW3C2B Datasheet - Page 20
NAND08GW3C2B
Manufacturer Part Number
NAND08GW3C2B
Description
8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.NAND08GW3C2B.pdf
(60 pages)
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5 Command set
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Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
Program and Erase operations are imposed to maximize data security.
The commands are summarized in
Table 7.
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
Page Read
Read for copy-back
Read ID
Reset
Page Program
Multiplane Page Program
Copy-back Program
Multiplane Copy Back Program
Block Erase
Multiplane Block Erase
Read Status Register
Random Data Input
Random Data Output
input/output data are not shown.
Command
Commands
1
st
FFh
00h
00h
90h
80h
80h
85h
85h
60h
60h
70h
85h
05h
cycle
Table 7:
2
Bus write operations
Commands.
nd
D0h
E0h
30h
35h
10h
11h
10h
11h
60h
cycle
NAND08GW3C2B, NAND16GW3C4B
3
rd
D0h
81h
81h
cycle
(1)
4
th
10h
10h
cycle
during busy
Commands
accepted
Yes
Yes
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