HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 713

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HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Reset in T
T
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus outputs are held during the T
occurs in the T
3
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
ø
RES
Internal
reset signal
Address bus
CS
CS to CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
3
State: Figure D-3 is a timing diagram for the case in which RES goes low during the
1
Figure D-3 Reset during Memory Access (Reset during T
2
state of an access cycle to a two-state-access area.
Access to external address
T
1
695
3
state.The same timing applies when a reset
T
2
T
3
3
State)
High impedance
High impedance
High impedance
H'000000

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