HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 234

• Manufacturer Part Number: HD6413003RVF
• Description: microcontroller (MCU)
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4.8 DMAC Bus Cycle
Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
Figure 8-14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
ø
A
RD
HWR
LWR
23
to A
0
T
1
CPU cycle
T
2
Figure 8-13 DMA Transfer Bus Timing (Example)
T
1
T
2
T
d
T
Source
address
1
DMAC cycle (word transfer)
T
2
216
T
1
T
Destination address
2
T
d
3
), it reads from the source address and
T
1
T
2
T
3
T
1
T
CPU cycle
2
T
1
T
2