HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 712

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HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Reset in T
T
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. The same timing applies when a reset occurs during a wait state (T
2
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
ø
RES
Internal
reset signal
Address bus
CS
CS to CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
2
State: Figure D-2 is a timing diagram for the case in which RES goes low during the
1
Figure D-2 Reset during Memory Access (Reset during T
Access to external address
T
1
694
T
2
T
3
H'000000
W
2
State)
).
High impedance
High impedance
High impedance

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