HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 414

• Manufacturer Part Number: HD6413003RVF
• Description: microcontroller (MCU)
• Manufacturer: RENESAS [Renesas Technology Corp]

11.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see
section 11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit
Initial value
Read/Write
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP )
—
—
7
1
15
11
7
3
Reserved bits
—
—
6
1
to TP )
to TP )
4
0
12
8
—
—
5
1
396
—
—
4
1
G3NOV
R/W
3
0
G2NOV
R/W
2
0
G1NOV
R/W
1
0
G0NOV
R/W
0
0