HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 11

• Manufacturer Part Number: HD6413003RVF
• Description: microcontroller (MCU)
• Manufacturer: RENESAS [Renesas Technology Corp]

10.3
10.4
10.5
10.6
Section 11
11.1
11.2
11.3
10.2.11 Timer I/O Control Register (TIOR)................................................................ 310
10.2.12 Timer Status Register (TSR)........................................................................... 312
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 315
CPU Interface ................................................................................................................. 317
10.3.1
10.3.2
Operation ........................................................................................................................ 321
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
Interrupts ........................................................................................................................ 362
10.5.1
10.5.2
10.5.3
Usage Notes .................................................................................................................... 366
Overview ........................................................................................................................ 381
11.1.1
11.1.2
11.1.3
11.1.4
Register Descriptions...................................................................................................... 385
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.2.10 TPC Output Mode Register (TPMR).............................................................. 396
Operation ........................................................................................................................ 398
11.3.1
16-Bit Accessible Registers ............................................................................ 317
8-Bit Accessible Registers .............................................................................. 319
Overview......................................................................................................... 321
Basic Functions............................................................................................... 322
Synchronization .............................................................................................. 332
PWM Mode .................................................................................................... 334
Reset-Synchronized PWM Mode ................................................................... 338
Complementary PWM Mode.......................................................................... 341
Phase Counting Mode..................................................................................... 351
Buffering......................................................................................................... 353
ITU Output Timing......................................................................................... 360
Setting of Status Flags .................................................................................... 362
Clearing of Status Flags.................................................................................. 364
Interrupt Sources and DMA Controller Activation ........................................ 365
Programmable Timing Pattern Controller
Features........................................................................................................... 381
Block Diagram................................................................................................ 382
TPC Pins ......................................................................................................... 383
Registers ......................................................................................................... 384
Port A Data Direction Register (PADDR) ...................................................... 385
Port A Data Register (PADR) ......................................................................... 385
Port B Data Direction Register (PBDDR) ...................................................... 386
Port B Data Register (PBDR) ......................................................................... 386
Next Data Register A (NDRA)....................................................................... 387
Next Data Register B (NDRB) ....................................................................... 389
Next Data Enable Register A (NDERA) ........................................................ 391
Next Data Enable Register B (NDERB)......................................................... 392
TPC Output Control Register (TPCR)............................................................ 393
Overview......................................................................................................... 398
......................................... 381