HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 243

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HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
8.4.10 External Bus Requests, Refresh Controller, and DMAC
During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8-21 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
ø
A
RD
HWR
23
to A
,
LWR
0
T
1
Figure 8-21 Bus Timing of Refresh Controller and DMAC
T
2
DMAC cycle (channel 0)
T
1
T
2
T
1
T
2
T
1
225
T
2
T
Refresh
cycle
1
T
2
T
d
T
DMAC cycle (channel 0)
1
T
2
T
1
T
2
T
1
T
2

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