HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 236

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HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode
and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the
pin is next sampled at the end of one block transfer.
Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
ø
A
RD
HWR
23
to A
,
LWR
0
CPU cycle
T
1
T
2
T
d
T
1
Source
address
Figure 8-15 Burst DMA Bus Timing
T
2
T
Destination
address
1
T
2
T
218
DMAC cycle
1
T
2
T
1
T
2
T
1
T
2
T
1
T
2
T
CPU cycle
1
T
2

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