HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 192

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HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
8.1.2 Block Diagram
Figure 8-1 shows a DMAC block diagram. The DMAC is divided into two groups (group 0 and
group 1) of four channels each.
Internal
interrupts
Interrupt
signals
Legend
DTCR:
MAR:
IOAR:
ETCR:
Data transfer control register
Memory address register
I/O address register
Execute transfer count register
Figure 8-1 Block Diagram of DMA Controller (Group 0: Four Channels)
DEND0A
DEND0B
DEND1A
DEND1B
DREQ0
DREQ1
TEND0
TEND1
IMIA0
IMIA1
IMIA2
IMIA3
RXI0
TXI0
Data buffer
Control logic
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Internal address bus
Internal data bus
Channel
Channel
174
0
1
Channel
Channel
Channel
Channel
0A
0B
1A
1B
Arithmetic-logic unit
Address buffer
MAR0A
MAR0B
MAR1A
MAR1B
ETCR0A
ETCR0B
ETCR1A
ETCR1B
IOAR0A
IOAR0B
IOAR1A
IOAR1B

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