HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 878

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.1.2
The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration.
Table 20.1 Clock Pulse Generator Register
Name
System clock control register
Note: * Lower 16 bits of the address.
20.2
20.2.1
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Rev.4.00 Sep. 07, 2007 Page 848 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Register Configuration
Register Descriptions
System Clock Control Register (SCKCR)
Normal Operation
φ output (Initial value)
Fixed high
:
:
PSTOP
R/W
7
0
R/W
—
6
0
Abbreviation
SCKCR
Sleep Mode
φ output
Fixed high
R/W
DIV
5
0
Description
—
—
4
0
R/W
R/W
Software
Standby Mode
Fixed high
Fixed high
—
—
0
3
Initial Value
H'00
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
SCK1
R/W
1
0
Address *
H'FF3A
SCK0
R/W
0
0