HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 613

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.2.2
Note: * Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable * register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in
interval timer mode. This flag cannot be set during watchdog timer operation.
Bit 7
OVF
0
1
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF
signal when TCNT overflows.
Bit 6
WT/IT
0
1
Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3,
Bit
Initial value :
R/W
Reset Control/Status Register (RSTCSR).
section 13.2.4, Notes on Register Access.
Timer Control/Status Register (TCSR)
Description
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode
Description
when TCNT overflows
[Clearing condition]
[Setting condition]
Interval timer: Sends the CPU an interval timer interrupt request (WOVI)
Watchdog timer: Generates the WDTOVF signal when TCNT overflows*
:
:
R/(W) *
OVF
7
0
WT/IT
R/W
6
0
TME
R/W
5
0
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—
1
4
Rev.4.00 Sep. 07, 2007 Page 583 of 1210
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—
3
1
CKS2
R/W
2
0
REJ09B0245-0400
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0