HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 172

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area partition unit, enabling or disabling of the write data buffer
function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus-released state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Bit 5—External Address Enable (EAE): Designates addresses H'010000 to H'03FFFF *
either internal or external addresses.
Rev.4.00 Sep. 07, 2007 Page 142 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bus Control Register L (BCRL)
:
:
Description
External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
External bus release enabled
Description
BREQO output disabled. BREQO pin can be used as I/O port
BREQO output enabled
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
R/W
—
4
1
DDS
R/W
1
3
R/W
—
2
1
WDBE
R/W
1
0
(Initial value)
(Initial value)
2
WAITE
as
R/W
0
0