HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 200

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.5.6
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is
four states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling
or disabling of wait insertion, and do not affect the number of access states. When the
corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access
cycle.
The four states of the basic timing consist of one T
output cycle) state, and the T
Rev.4.00 Sep. 07, 2007 Page 170 of 1210
REJ09B0245-0400
Read
Write
Note: n = 2 to 5
Basic Timing
A
CS
CAS, LCAS
HWR (WE)
D
HWR (WE)
D
φ
23
15
15
n
to A
to D
to D
(RAS)
0
0
0
c1
and T
Figure 6.15 Basic Access Timing
T
c2
p
(column address output cycle) states.
Row
p
T
(precharge cycle) state, one T
r
T
c1
Column
T
c2
r
(row address