HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 484

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and
cannot be modified.
Bit 4
BFA
0
1
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3
MD3 *
0
1
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.4.00 Sep. 07, 2007 Page 454 of 1210
REJ09B0245-0400
1
2. Phase counting mode cannot be set for channels 0 and 3. For these channels, 0 should
Bit 2
MD2 *
0
1
*
always be written to MD2.
Description
TGRA operates normally
TGRA and TGRC used together for buffer operation
2
Bit 1
MD1
0
1
0
1
*
Bit 0
MD0
0
1
0
1
0
1
0
1
*
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
(Initial value)
(Initial value)
*: Don’t care