HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 719

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Smart Card Interface
With the above processing, interrupt handling or data transfer by the DMAC or DTC is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt
(ERI) request will be generated.
If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred
is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred.
For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by
DMAC or DTC below.
If a parity error occurs during reception and the PER is set to 1, the received data is still
transferred to RDR, and therefore this data can be read.
Note: For details of operation in block transfer mode, see section 14.3.2, Operation in
Asynchronous Mode.
Mode Switching Operation: When switching from receive mode to transmit mode, first confirm
that the receive operation has been completed, then start from initialization, clearing RE bit to 0
and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the
receive operation has been completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The
TEND flag can be used to check that the transmit operation has been completed.
Fixing Clock Output: When the GM bit in SMR is set to 1, the clock output can be fixed with
bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the
specified width.
Figure 15.8 shows the timing for fixing the clock output. In this example, GM is set to 1, CKE1 is
cleared to 0, and the CKE0 bit is controlled.
Rev.4.00 Sep. 07, 2007 Page 689 of 1210
REJ09B0245-0400