HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 15

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.6
6.7
6.8
6.9
6.10 Bus Release....................................................................................................................... 194
6.11 Bus Arbitration.................................................................................................................. 197
6.12 Resets and Bus Controller................................................................................................. 199
Section 7 DMA Controller
7.1
7.2
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 176
6.5.11 Refresh Control.................................................................................................... 179
DMAC Single Address Mode and DRAM Interface ........................................................ 183
6.6.1
6.6.2
Burst ROM Interface......................................................................................................... 185
6.7.1
6.7.2
6.7.3
Idle Cycle .......................................................................................................................... 188
6.8.1
6.8.2
Write Data Buffer Function .............................................................................................. 193
6.10.1 Overview.............................................................................................................. 194
6.10.2 Operation ............................................................................................................. 194
6.10.3 Pin States in External-Bus-Released State ........................................................... 195
6.10.4 Transition Timing ................................................................................................ 196
6.10.5 Usage Note........................................................................................................... 197
6.11.1 Overview.............................................................................................................. 197
6.11.2 Operation ............................................................................................................. 197
6.11.3 Bus Transfer Timing ............................................................................................ 198
6.11.4 External Bus Release Usage Note........................................................................ 198
Overview........................................................................................................................... 201
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 207
7.2.1
7.2.2
7.2.3
Precharge State Control ....................................................................................... 171
Wait Control ........................................................................................................ 172
Byte Access Control ............................................................................................ 174
When DDS = 1..................................................................................................... 183
When DDS = 0..................................................................................................... 184
Overview.............................................................................................................. 185
Basic Timing........................................................................................................ 185
Wait Control ........................................................................................................ 187
Operation ............................................................................................................. 188
Pin States in Idle Cycle ........................................................................................ 192
Features................................................................................................................ 201
Block Diagram..................................................................................................... 202
Overview of Functions......................................................................................... 203
Pin Configuration................................................................................................. 205
Register Configuration......................................................................................... 206
Memory Address Registers (MAR) ..................................................................... 208
I/O Address Register (IOAR) .............................................................................. 209
Execute Transfer Count Register (ETCR) ........................................................... 209
................................................................................................ 201
Rev.4.00 Sep. 07, 2007 Page xv of xxx