PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 208

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Note: If only one short FSC pulse is needed, this bit should be reset to '0' by the DELIC
6.2.11.9 L1_CLK Control Register
L1_CLK Control Register (CL1CLK)
Reset value: 0000
Note: ’x’ = unused bits, read as 0.
L1CLKEN L1_CLK Disable
L1CLK
Preliminary Data Sheet
software, after the next FSC rising edge detection (after the begining of the next
frame). It is not executed automatically by the hardware.
15
7
x
x
1 =
0 =
1 =
L1_CLK Clock Rate
0 =
1 =
H
14
6
x
x
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000
L1_CLK is enabled (default)
L1_CLK is disabled
7.68 MHz (default)
15.36 MHz
13
x
5
x
12
x
4
x
read/write
6-68
11
x
3
x
10
2
x
x
Register Description
L1CLKDIS L1CLK
Address: D088
9
x
1
DELIC
2003-08
8
x
0
H