PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 109

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PEB20571

Manufacturer Part Number
PEB20571
Description
ICs for Communications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet

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Figure 4-4 shows the PCM interface timing with single and double rate PDC.
Figure 4-10 IOM-2 Interface Timing in Single/Double Clock Mode
4.4.1.5
The incoming serial data is converted into parallel bytes, and stored in the I-buffer input
blocks. The sequence for every time slot received is from MSB (bit 7) to LSB (bit 0).
Transmission is performed from MSB (bit 7) to LSB (bit 0).
4.4.1.6
The data read from the PCMU frame buffers by the DSP always reside in the low byte of
the 16-bit word. The high byte of the read word is driven by the 8-bit PCMU Data Prefix
Register (PDPR). The data prefix is used to accelerate the A-/µ-law to linear conversions
(refer to Chapter 4.5).
Preliminary Data Sheet
PFS
PDC
TXD
RXD
PFS
PDC
TXD
RXD
TS31
bit0
PCMU Serial Data Processing
PCMU Parallel Data Processing
TS31
TS31
TS31
bit0
bit0
bit0
Frame Start
TS0
Frame Start
bit7
TS0
bit7
= data Sampling
TS0
bit7
TS0
TS0
bit6
bit7
TS0
bit6
TS0
bit5
TS0
bit5
TS0
bit6
4-25
TS0
TS0
bit4
bit6
TS0
bit4
Double Data Rate PDC
Single Data Rate PDC
TS0
bit3
TS0
bit3
= PFS Sampling
TS0
bit5
TS0
TS0
bit2
bit5
TS0
bit2
Functional Description
TS0
bit1
TS0
bit1
TS0
bit4
TS0
TS0
bit0
bit4
TS0
bit0
PEB 20571
TS1
bit7
TS1
bit1
DELIC
2003-08

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