PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 207

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

DCL(2:0) DCL Clock Rate
6.2.11.8 FSC Control Register
FSC Control Register (CFSC)
Reset value: 0002
Note: ’x’ = unused bits, read as 0.
FSCEN
FSCSH
EFSCD
IFSCD
Preliminary Data Sheet
15
7
x
x
1 =
000 =
001 =
010 =
011 =
100 =
FSC Clock Enable
0 =
1 =
Short FSC Pulse
0 =
1 =
External FSC Delay
0 =
1 =
Internal FSC Delay (only valid of CSTRAP: bit0 = 1)
0 =
H
14
6
DCL is enabled (default)
384 kHz
768 kHz
1536 kHz
2048 kHz (default)
4096 kHz
x
x
FSC is disabled (stuck at '0')
FSC is enabled (default)
The next FSC pulse will be longer than 2 DCL cycles (default)
The next FSC pulse will be shorter than 2 DCL cycles (short FSC)
no delay between FSC and DCL rising edge
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000
no delay between FSC and DCL rising edge
13
5
x
x
12
x
4
x
read/write
6-67
IFSCD
11
x
3
EFSC
10
2
x
Register Description
FSCEN
Address: D087
9
1
x
FSCSH
DELIC
2003-08
8
x
0
H