PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 173

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.5
6.2.5.1
In order to enable DSP access all the buffers and RAMS, DSPCTRL bit must be set to ‘1’.
HCR Register
Reset value: 0001
HPRS(5:0)
DSPCTRL
Note: Each time DSPCTRL is set, HPRS is also set.
Preliminary Data Sheet
15
7
x
x
HDLCU Registers Description
HDLCU Control Register
HDLCU Channel Preset
The number of HDLC channels to be processed by the HDLCU
DSP Access Control to the HDLCU
0 =
1 =
H
14
6
x
The DSP must not access the HDLCU buffers and RAMs
The DSP may access the HDLCU buffers
13
5
x
12
HPRS(5:0)
x
4
write
6-33
11
x
3
10
2
x
Register Description
9
1
x
Address: D180
DSPCTRL
DELIC
2003-08
8
0
x
H