PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 162

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Note: Both values ’0’ or ’1’ written to SCSTA will start the scrambling
6.2.2
6.2.2.1
ICR Register
Reset value: 02
ICDB
A
OD
DC
Preliminary Data Sheet
15
7
x
x
1 =
IOMU Register Description
IOMU Control Register
Idle Current D-Buffer ( for test purpose; only if IOMU is in idle mode: ICR:A
= ’0’)
0 =
1 =
IOMU Activation
0 =
1 =
DD0 and DD1 Output Mode
0 =
1 =
Double Data Rate Clock
0 =
H
14
6
x
x
Write access: start of scrambling algorithm for all channels enabled
in the HRAM
read access: scrambling has finished
Make frame buffer 0 accessible to the DSP
Make frame buffer 1 accessible to the DSP
The IOMU is Idle. The state machine of the IOMU is idle, and no
accesses to the I-buffer are executed by the IOMU.
The IOMU is active, and works according to the programming of the
other Control Register bits.
Push-Pull mode.
Open-Drain mode
Single clock (DCL frequency is identical to the IOM-2 data rate)
ICDB
13
x
5
12
A
x
4
read/write
6-22
OD
11
3
x
DC
10
2
x
Register Description
Address: D040
9
1
x
DR(1:0)
DELIC
2003-08
8
x
0
H