PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 167

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.3
6.2.3.1
PCR Register
Reset value: 0000
PDR(1:0) PCM Data Rate
PDCL
PA
ICDB
SFH
Preliminary Data Sheet
15
7
x
x
PCMU Register Description
PCMU Command Register
00 =
01 =
10 =
11 =
PCM Double Data Rate Clock
0 =
1 =
PCMU Activation
0 =
1 =
Idle Current D-Buffer
Used only for testing of PCMU in IDLE mode (PCR:PA = '0') to determine
which buffer is being accessed by the DSP
0 =
1 =
Second Frame Half
Used only in 1 x 256 time slots per frame data rate mode
0 =
H
14
6
x
x
4 x 2.048 Mbit/s (4 x 32 time slots per frame)
2 x 4.096 Mbit/s (2 x 64 time slots per frame)
1 x 8.092 Mbit/s (1 x 128 time slots per frame)
1 x 16.384 Mbit/s (1 x 256 time slots per frame, if only first or
second half of 8 kHz frame is handled)
Single Data Rate Clock
Double Data Rate Clock
The PCMU is in idle mode
The PCMU is in active mode
Frame buffer 0 is accessed by the DSP
Frame buffer 1 is accessed by the DSP
The first 128 time slots of each frame are handled by the PCMU
SFH
13
x
5
ICDB
12
x
4
read/write
6-27
PA
11
3
x
PDCL
10
2
x
Register Description
Address: D060
9
1
x
PDR(1:0)
DELIC
2003-08
8
x
0
H