PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 134

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
4.12
4.12.1
The DELIC clock generator provides all necessary clock signals for the DELIC and
connected clock slave devices. The internal clocks are generated by two on-chip PLLs:
1. A digital controlled oscillator (DCXO) generates a 16.384 MHz clock from an external
2. A PLL multiplies the 16.384 MHz clock to a 61.44 MHz clock.
An overview of the clock signals and a block diagram is shown below.
Table 4-15
Pin
CLK16-XI
CLK16-XO 16.384 MHz External Crystal Output
XCLK
REFCLK
PFS
PDC
CLKOUT
DCL_2000 IOM-2000 Data Clock (3.072, 6.144 or 12.288 MHz)
DCL
FSC
L1_CLK
DSP_CLK
crystal.
Clock Generator
Overview
Function
16.384 MHz External Crystal Input
External Reference Clock from layer-1 IC
(2.048 MHz, 1.536 MHz or 8 kHz)
PCM Reference Clock (8 kHz or 512 kHz)
PCM Frame Synchronization 8 kHz (I/O) or 4 kHz (I) I/O I (Slave)
PCM Data Clock (2.048, 4.096, 8.192 or 16.384 MHz) I/O I (Slave)
Auxiliary Clock
(2.048, 4.096, 8.192, 16.384, or 15.36 MHz)
IOM-2 Data Clock
(384 kHz, 768 kHz, 2.048 MHz or 4.096 MHz)
IOM-2 and IOM-2000 Frame Synchronization 8 kHz. O
Layer-1 Clock 15.36 or 7.68 MHz
(e.g. OCTAT-P / QUAT-S)
DSP Test Clock.
(to run the DSP at clock rates other than 61.44 MHz)
Overview of Clock Signals
4-50
Functional Description
I/O During Reset
I
O
I
I/O tristate
O
O
O
O
I
I
O
I
(1.536 MHz)
O (Master)
O (Master)
(2.048 MHz)
O
(2.048 MHz)
O
(3.072 MHz)
O
(384 kHz)
O
O
(7.68 MHz)
I
DELIC
2003-08