PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 114

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
4.6
4.6.1
The HDLCU decodes and encodes HDLC messages to and from the DSP. It may
process up to 32 full-duplex HDLC channels in parallel. It is controlled by the DSP
through software and is thus very flexible.
The HDLCU includes a Receive Input Buffer, a Receive Output Buffer, a Transmit Input
Buffer and a Transmit Output Buffer, some HDLC protocol processing logic and a
command RAM.
Figure 4-11 HDLCU General Block Diagram
Figure 4-11 shows the HDLCU structure. Each buffer, except the Transmit Output
Buffer, is a 32 x 8 RAM, hence one byte is assigned to each HDLC time slot channel.
Receive Output Buffer
Receive Input Buffer
32 channels
encoded
decoded
32 channels
DSP data double buffer
HDLC Unit
HDLCU Unit Overview
DSP D-Buffer*
Processing
Internal
32x8
32x8
DSP Control
command
32x8
RAM
4-30
Processing
32x16
Internal
DSP D-Buffer*
32x8
DSP Data Double Buffer
Transmit Output Buffer
Transmit Input Buffer
Functional Description
32 channels
32 channels
* Frame-buffers of the IOMU,
PCMU or TRANSIU that belong to
the DSP during the present frame
DELIC
2003-08