PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 131

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

number of bytes to be transferred the last byte is available on the least significant byte
of the last word in FIFO.
Note: TX_BSY is not an indication for the transaction partners. It may be used for
Data Transfer via the Transmit Mailbox
• The OAK writes to TX_CREG.
• DREQT is asserted (’high’), and TX_BSY bit is set (’1’).
• The DMA asserts DACK = 0 and issues TX_CREG write transactions to the Mailbox.
• DREQT is deasserted (’low’), and TX_BSY bit is reset (’0’).
• If TX_MASK bit is reset (’0’): an OAK interrupt (INT1) is activated.
• The OAK reads the TX_REG bytes in the Mailbox and transfers them to the GHDLC.
Note: 1. The OAK must not write to the TX_CREG reg before TX_BSY is reset.
4.10.6
The Receive Mailbox includes:
• 18-byte FIFO which is accessed by the OAK (for write) as 9 “regular” addressed 16-
• 5-bit counter for the general number of transactions in current transfer (RX_CREG).
• 5-bit counter for number of transactions that remains in the transfer (RX_CNT).
• 1-bit status register (RX_STAT).
Like in the Transmit Mailbox, the OAK is always the master of this transfer, i.e. the
transfer is initiated by the OAK, but controlled by DMA.
When the OAK requests a transfer of data from the high-speed GHDLC channel, it writes
this data to the Receive Mailbox, the first byte to the least significant byte of the least
significant word. Note that in case of odd number of bytes, the most significant byte of
the last word is don’t care.
Then, the OAK writes the number of bytes needed to the RX_CREG register which sets
RX_BSY bit, and causes the assertion of DREQR (“DMA Request Receive”) pin.
If DMA grants the bus to OAK, it drives DACK low and begins toggling the control lines.
In Intel/Siemens (Mem-to-Mem) mode it drives RD line low when it reads from the
Mailbox and high when it writes to the memory. WR line stays high during the complete
transfer, because there are no ‘Write’ operations from here. DACK is low all the time. In
Motorola (Mem-to-Mem) mode it drives R/W line high for ‘Read’ operations when DACK
and DS are low; when DMA refers to the external memory, it drives DS high.
Note that in Fly-by mode the meaning of ‘Read’ and ‘Write’ commands is opposite for the
Mailbox. After each ‘Read’ operation the counter (RX_CNT) is decremented by one. If
Preliminary Data Sheet
bit wide registers, and by the DMA (for read) like a FIFO. One of the nine registers is
a “special” register like in the General Mailbox and has 3 addresses associated with it.
internal software needs of the OAK.
2. Writing’0’ to TX_CREG is not allowed.
Receive Mailbox
4-47
Functional Description
PEB 20571
DELIC
2003-08