PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 175

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.5.3
HCCV Registers
Each of the 32 HDLC channels has a 7-bit command vector that resides in the
corresponding address of the command RAM. The structure of a command vector is as
follows:
Note: Accesses to these registers are possible only if register bit HCR:DSPCTRL = 1
DBSEL
RECRES
TXCMD(2:0)
CRC
Preliminary Data Sheet
’x’ = unused
15
7
x
x
Channel Command Vector
D- or B-Channel Select
0 =
1 =
Receiver Reset
0 =
1 =
Transmit Command
000=
001=
010=
011=
100=
CRC Enable
0 =
DBSEL
14
6
x
Indication for a B-channel. HDLC protocol is performed on all 8
data bits
Indication for a D-channel. HDLC protocol is performed only on
the 2 MSB data bit in the Receive Input Buffer and Transmit
Output Buffer
Normal operation
Reset the HDLC receiver
End transmition
Start transmission at the first bit of the D-channel
Start transmission at the second bit of the D-channel
Start transmitting a flag (beginning with the fifth bit of the flag,
since ’0111’ is automatically inserted)
Abort transmission
Note: other combinations are reserved
CRC checking algorithm off
RECRES
13
x
5
read/ write
12
4
x
6-35
TXCMD(2:0)
11
3
x
Addresses:
10
2
x
Register Description
CRC
9
x
1
4040
H
- 405F
IDLE
DELIC
2003-08
8
0
x
H