m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 93

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m30833fjgp

Manufacturer Part Number
m30833fjgp
Description
Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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R
R
M
e
E
3
. v
J
Figure 8.5 CM2 Register
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
o r
n
Oscillation Stop Detect Register
b7
0
NOTES:
3 .
1
u
3
, 1
p
1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the main clock oscillation stop is detected while the CM20 bit is set to "1" (oscillation stop
3. When the CM20 bit is set to "1" (oscillation stop detect function enabled) and the CM22 bit is set to "1", do
4. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0",
5. Determine the main clock state by reading the CM23 bit several times after the oscillation stop
0
b6
1
(
2
detect function enabled), the CM21 bit is set to "1". Although the main clock starts oscillating, the
CM21 bit is not set to "0". When the main clock is used as a CPU clock source after the main clock
resumes oscillation, set the CM21 bit to "0" by program.
not set the CM21 bit to "0".
not "1", by program.
If the CM22 bit is set to "0" by program while the main clock is stopped, the CM22 bit cannot be set to
"1" until the next main clock stop is detected.
interrupt is generated.
M
0
b5
0
0
3
6
2
b4
0
C
8 /
b3
Page 70
, 3
b2
M
b1
3
2
C
b0
f o
8 /
4
3
(b7 - b4)
8
Symbol
CM20
CM21
CM22
CM23
) T
8
Bit
Symbol
CM2
Oscillation Stop Detect
Enable Bit
CPU Clock Select Bit
Oscillation Stop Detect
Flag
X
Reserved Bit
IN
Clock Monitor Flag
(4)
Bit Name
(1)
Address
000D
16
(2, 3)
(5)
0: Disables oscillation stop detect function
1: Enables oscillation stop detect function
0: Clock selected by the CM17 bit
1: On-chip oscillator clock
0: Main clock does not stop
1: Detects main clock stop
0: Main clock oscillates
1: Main clock stops
Set to "0"
After Reset
00
16
Function
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RO

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