m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 498

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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27.10 Serial I/O
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27.10.1 Clock Synchronous Serial I/O Mode
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27.10.1.1 Transmission / Reception
27.10.1.2 Transmission
27.10.1.3 Reception
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When the RTS function is used while an external clock is selected, the output level of the RTSi pin is
held low ("L") indicating that the microcomputer is ready for reception. The transmitting microcomputer
is notified that reception is possible. The output level of the RTSi pin becomes high ("H") when recep-
tion begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer
synchronizes transmission and reception. The RTS function is disabled if an internal clock is selected.
The RTS
NMI pin while the INV02 to INV01 bits in the INVC0 register are set to "11
phase output by low-level signal ("L") applied to NMI pin).
When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the
following conditions:
• Set the TE bit in the UiC1 register to "1" (transmit enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiBT register)
• Apply "L" signal to the CTSi pin if the CTS function is selected
Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore,
set for transmission even if the microcomputer is used for reception only. Dummy data is output from
the TxDi pin while receiving.
If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1(i=0 to 2)
registers is set to "1" (receive enable) and dummy data is set in the UiTB register. If an external clock
is selected, the shift clock is generated when the external clock is input into CLKi pin while the TE bit
is set to "1" (receive enable) and dummy data is set in the UiTB register.
When receiving data consecutively while the RE bit in the UiC1(i=0 to 2) register is set to "1" (data in
the UiRB register) and the next data is received by the UARTi reception register, an overrun error
occurs and the OER bit in the UiRB register becomes "1" (overrun error). In this case, the UiRB
register is indeterminate. When overrun error occurs, program both reception and transmission regis-
ters to retransmit earlier data. The IR bit in the SiRIC does not change when an overrun error occurs.
When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every
time a reception is made.
When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the
following conditions:
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• Set the RE bit in the UiC1 register to "1" (receive enabled)
• Set the TE bit in the UiC1 register to "1" (transmit enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
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pin and CLK
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pin are placed in high-impedance states when an "L" signal is applied to the
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27. Precautions (Serial I/O)
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