m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 211

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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16.2 Clock Asynchronous Serial I/O (UART) Mode
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Table 16.6 UART Mode Specifications
2
0
Transmit/Receive Control
NOTES:
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Generation Timing
Error Detect
Selectable Function
In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format.
Table 16.6 lists specifications of UART mode.
1
9
C
3 .
B
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged
8 /
0
1
as "1" (interrupt requested).
3
0
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Page 188
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• Character bit (transfer data ) : selected from 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selected from odd, even, or none
• Stop bit: selected from 1 bit or 2 bits long
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected) :
• The CKDIR bit is set to "1" (external clock selected) :
• Select from CTS function, RTS function or CTS/RTS function disabled
• To start transmitting, the following requirements must be met:
• To start receiving, the following requirements must be met:
• Transmit interrupt timing can be selected from the followings:
• Receive interrupt timing
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first / MSB first
•Serial data logic inverse
•TxD, RxD I/O polarity switching
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Apply an "L" signal to the CTSi pin when the CTS function is selected
- Set the RE bit in the UiC1 register to "1" (receive enable)
- The start bit is detected
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) :
- The UiIRS bit is set to "1" (transmission completed) :
This error occurs when the bit before the last stop bit of the next received data is read
prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
This error occurs when the number of stop bits set is not detected
When parity is enabled, this error occurs when the number of "1" in parity and character
bits does not match the number of "1" set
This flag is set to "1" when any of an overrun, framing or parity errors occur
Data is transmitted or received in either bit 0 or in bit 7
Logic values of data to be transmitted or received data are inversed. The start bit and
stop bit are not inversed
TxD pin output and RxD pin input are inversed
3
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
when data transmission from the UARTi transfer register is completed
2
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EXT
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/16(m+1) f
f o
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4
/16(m+1)
3
8
) T
8
_______
(2)
j
= f
1
, f
8
, f
2n (1)
f
EXT
_______
_______
: clock applied to the CLKi pin
m: setting value of the UiBRG register 00
Specification
_______ _______
_______
16. Serial I/O (UART)
16
to FF
16