m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 146

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
12.2 DMAC Transfer Cycles
12.3 Channel Priority and DMA Transfer Timing
3
. v
J
i= 0 to 3, p = 0 to 1
Table 12.3 DMAC Transfer Cycles
Table 12.4 Coefficient j, k
2
0
n I
n I
k
w
= j
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer Unit
8-bit transfers
(BWi bit in the DMDp
16-bit transfers
(BWi bit = 1)
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external factors.
In Figure 12.7, the DMA0 request having the highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
1
C
9
register = 0)
e t
e t
h t i
=
3 .
B
8 /
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
1
n r
n r
1
0
1
n
3
0
l a
l a
o
3
J
G
R
R
w
4
a
0 -
n
o r
O
A
i a
3 .
M
s t
M
1
u
, 1
3
p
a t
r o
1
e t
2
(
n I
M
0
e t
0
3
n I
n I
a
k
= j
6
n r
2
e t
e t
=
w
l a
C
2
n r
n r
i a
2
8 /
Page 123
S
s t
l a
l a
p
, 3
a
a t
Bus Width Access Address
R
R
e c
e t
O
A
16-bit
16-bit
M
8-bit
8-bit
M
M
3
w
2
r o
C
h t i
f o
8 /
4
3
8
k
S
A
= j
) T
8
F
e r
=
R
2
a
2
B
S
w
k
= j
Even
Even
Even
Even
Odd
Odd
Odd
Odd
s u
e
i a
=
p
1
s t
2
a
w
a r
a t
h t i
e t
e t
n
o
B
k
S
w
j
s u
=
e
i a
=
p
s t
2
Cycle
a
2
Read
w
a r
a t
Single-Chip Mode
—
—
—
—
h t i
1
1
1
2
e t
e t
1
S
B
k
w
j
e
s u
=
i a
=
p
s t
3
a
3
w
E
a r
t a t
h t i
x
e t
r e t
Cycle
Write
s e
2
a n
—
—
—
—
1
1
1
2
S l
S
B
k
w
j
a p
s u
e
=
i a
=
p
s t
e c
4
a
4
w
a r
t a t
h t i
e t
Memory Expansion Mode
s e
3
Microprocessor Mode
Cycle
Read
M
B
k
w
j
1
1
1
1
1
2
2
2
s u
=
i a
l u
=
s t
p i t
3
3
w
e l
t a t
h t i
e x
s e
2
d
Cycle
Write
M
B
k
w
j
s u
=
l u
i a
=
1
1
1
1
1
2
2
2
s t
p i t
12. DMAC
4
4
w
e l
t a t
h t i
e x
s e
3
d