m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 301

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
2
0
Table 21.10 Phase-delayed Waveform Output Mode Specifications
Waveform Output Start Condition
Waveform Output Stop Condition
Interrupt Request
OUTC1j Pin
Selectable Function
NOTES:
Output Waveform
21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3)
1
9
C
3 .
B
Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) is inversed every time the value of the base timer
matches that of the GiPOj register. Table 21.10 lists specifications of phase-delayed waveform mode.
Figure 21.25 shows an example of phase-delayed waveform mode operation.
1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by
2. OUTC0
8 /
0
1
3
0
(OUTC1
both time measurement function and waveform generation function
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
0
Item
1
, OUTC0
0
2
(
to OUTC1
M
0
0
3
6
2
C
Page 278
8 /
1
, OUTC0
, 3
7
pins when using group 0 and group 1 cascaded connection)
M
3
2
C
4
f o
(1)
, OUTC0
8 /
4
3
8
• Free-running operation
• The base timer is reset by matching the base timer with the GiPO0 register
The IFEj bit (j=0 to 7) in the GiFE register is set to "1" (channel j function
enabled)
The IFEj bit is set to "0" (channel j function disabled)
The POijR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOj register. (See
Figure 10.14)
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
• Cascaded connection function: Connect group 0 and group 1 to operate as a
) T
8
(the RST2 to RST0 bits in the GiBCR1 register (i=0 to 3) are set to "000
Cycle
"H" and "L" width
(the RST1 bit is set to "1", and the RST0 and RST2 bit are set to "0")
Cycle
"H" and "L" width
the OUTCij pin
32-bit base timer
Setting value of the GiPOj (j=0 to 7) register is 0000
n : setting value of the GiPO0 register, 0001
Setting value of the GiPOj (j=1 to 7) register is 0000
If GiPOj register
5
, OUTC1
0
to OUTC1
n+2, the output level is not inversed
:
:
:
:
7
21. Intelligent I/O (Waveform Generation Function)
2(n+2)
65536 x 2
, OUTC2
f
n+2
f
65536
BTi
BTi
f
f
BTi
BTi
Specification
0
to OUTC2
16
7
, and OUTC3
to FFFD
16
16
to FFFF
to FFFF
16
0
to OUTC3
16
16
2
")
7
pins