m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 431

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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25.3.7 Precautions in CPU Rewrite Mode
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25.3.7.1 Operating Speed
25.3.7.2 Prohibited Instructions
25.3.7.3 Interrupts
25.3.7.4 Reading and Writing Commands and Data
25.3.7.5 Reset
25.3.7.6 Access Prohibited
25.3.7.7 How to Access
25.3.7.8 Rewriting in the User ROM Area
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Set the MCD register to the following CPU clock before entering CPU rewrite mode .
When the PM12 bit in the PM register is set to "0" (no wait state), 6.25MHz or less
When the PM12 bit in the PM register is set to "1" (wait state), 12.5MHz or less
In CPU rewrite mode, programs cannot be executed, nor can interrupt vectors be read in the flash
memory. Execute the rewrite control program after the program is transferred to a space other than
the flash memory. (See Figure 25.5.)
The following instructions cannot be used because the CPU tries to read data in the flash memory: the
UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction.
Read or write 16-bit commands and data from or to even addresses in the user ROM area.
Reset is always enabled.
Write the FMR01 bit and FMR05 bit in a space other than the flash memory.
To set the FMR01 bit and FMR02 bits to "1", set to "1" immediately after setting to "0". Do not generate
an interrupt or a DMA transfer between the instruction to set the bits to "1" and the instruction to set the
bits to "0". Set the FMR01 bit to "1" after an "H" signal is applied to the P8
If the supply voltage drops while in CPU rewrite mode, when rewriting the block where the rewrite
control program is stored, the flash memory cannot be rewritten because the rewrite control program
is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O
mode or parallel I/O mode.
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the
• The NMI and watchdog timer interrupts are available since the FMR01 is forcibly reset when either
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
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interrupt occurs. Allocate the jump addresses for each interrupt service routine and write to the fixed
vector table. Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt
occurs. Execute the rewrite program again after exiting the interrupt routine.
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25. Flash Memory Version