m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 153

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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13.4 Transfer Modes
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13.3.2 Immediate Data Transfer
13.3.3 Calculation Transfer
In DMAC II, single and burst transfers are available. The BRST bit in MOD selects transfer method, either
the single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs
when COUNT is set to "0000
13.4.1 Single Transfer
13.4.2 Burst Transfer
13.4.3 Multiple Transfer
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The DMAC II transfers immediate data to a desired memory location. A fixed or relocatable address can
be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit imme-
diate data, write the data in the low-order byte of SADR (high-order byte is ignored).
After two memory data, or an immediate data and memory data are added together, the calculated result
is transferred to a desired memory location. SADR must have one memory location address to be calcu-
lated or immediate data. OADR must have the other memory location address to be calculated. Fixed or
relocatable address can be selected as source and destination addresses when using a memory +
memory calculation transfer. If the transfer source address is relocatable, the operation address also
becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address
when using an immediate data + memory calculation transfer.
For every transfer request factor, the DMAC II transfers one transfer unit of 8-bit or 16-bit data once.
When the source or destination address is relocatable, the DMAC II increments the address, after a
transfer, for the next transfer.
COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the inter-
rupt is acknowledged when COUNT reaches "0".
For every transfer request factor, the DMAC II continuously transfers data the number of times deter-
mined by COUNT. The DMAC II decrements COUNT every time a transfer occurs. The burst transfer
ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer
ends if using the end-of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.
The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-
to-memory transfer. One transfer request factor initiates multiple transfers. The CNT2 to CNT0 bits in
MOD selects the number of transfers from "001
CNT0 bits to "000
The transfer source and destination addresses for each transfer must be allocated alternately to ad-
dresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer,
burst transfer, end-of-transfer interrupt and chained transfer cannot be used.
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13. DMACII