m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 275

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
2
0
Figure 21.4 Intelligent I/O Group 3 Block Diagram
1
9
C
3 .
B
8 /
0
1
Request from communication function
ISCLK3
3
0
ISRxD3
BT3S
BTS
f
1
3
J
G
4
a
BCK1 to BCK0
0 -
11
n
o r
(1)
3 .
1
u
, 1
3
p
1
Request from group2
2
(
M
0
0
3
6
2
NOTES:
selector
C
Clock
1. In the 100-pin package, these pins are not connected to external pins.
2. Each register enters a reset state after the G3BCR0 register supplies the
Page 252
8 /
Transmit operation clock
Receive operation clock
clock.
Reset
DIV4 to DIV0
by 2(n+1)
, 3
Divider
M
3
2
C
Request by matching the base
timer with the G3PO0 register
f
BT3
f o
8 /
Group3 base
timer reset
4
3
8
G3PO0 register
G3PO1 register
G3PO2 register
G3PO3 register
G3PO4 register
G3PO5 register
G3PO6 register
G3PO7 register
) T
Base timer
8
G3MK4 register
G3MK5 register
G3MK6 register
G3MK7 register
Transmission
Reception
G3TB register
Polarity
inverse
IPOL
Overflow of the bit 15
in the base timer
Base timer interrupt request (BT3R)
Mode controller
Shift counter
Receive shift
register
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Mode controller
Transmit Shift
Shift counter
register
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G3BCR0 register
BTS : Bit in the G3BCR1 register
BT3S : Bit in the BTSR register
MOD2 to MOD0 : Bits in the G3POCRj register (j = 0 to 7)
OPOL, IPOL : Bits in the G3CR register
Real time port
output value
Polarity
inverse
(3)
OPOL
control
control
control
control
output
output
output
output
PWM
PWM
PWM
PWM
G3RB register
000 to 010, 100
000 to 010,
100
MOD2 to MOD0
MOD2 to MOD0
111
OUTC3
OUTC3
OUTC3
OUTC3
OUTC3
OUTC3
111
(PO3jR)
Waveform generation
interrupt request
(SIO3RR)
Receive interrupt
request
(SIO3TR)
Transmit interrupt
request
2
3
4
5
6
7
OUTC3
OUTC3
(3)
21. Intelligent I/O
(3)
(3)
(Note 1)
0
1
/ISTxD3
/ISCLK3
(1)