m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 288

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
2
0
Table 21.2 Base Timer Specifications (Continued)
Figure 21.16 Base Timer Block Diagram
Table 21.3 Base Timer Associated Register Settings
(for Time Measurement Function, Waveform Generation Function, and Communication Function)
G2BCR0
BTSR
GiBCR0
GiBCR1
GiBT
Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register).
GiPOCR0
GiPO0
GiFS
GiFE
i : Bit configurations and functions vary with each group
1
C
9
BTS bit in GiBCR1 register
Selectable Function
Register
3 .
BTiS bit in BTSR register
B
Apply "L" to the INT
8 /
Request from communication
function (Group2,3)
0
1
Matching with the GiPO0 register
3
0
3
J
G
4
a
Apply two-phase
pulse signal (
Group0,1)
0 -
n
o r
3 .
1
u
, 1
3
p
Other base timer reset
1
2
(
Item
M
-
-
BCK1 to BCK0
DIV4 to DIV0
IT
RST2 to RST1
BTS
UD1 to UD0
CAS
-
MOD2 to MOD0
-
FSC0
IFE0
0
0
3
6
i
2
pin (Group0,1)
f
C
1
8 /
Page 265
Bit
, 3
10
11
BCK1 to BCK0
M
3
2
C
f o
8 /
RST0
RST1
RST2
4
Supplies operation clock to the BTSR register. Set to "0111 1111
Set to "0000 0000
Select count source
Select divide ratio of count source
Selects the base timer interrupt
Select factors for a base timer reset
Used to start the base timer independently
Select how to count (Group 0 and 1)
Selects cascaded connection (Group 0 and 1)
Read or write base timer value
Set to "000
Set reset cycle
Set to "0" (waveform generation function)
Set to "1" (channel operation start)
3
8
) T
8
• Two-phase pulse processing mode (Group 0 and 1)
and P8
by 2(n+1)
Divider
Two-phase pulse signals from P7
P7
P7
2
1
" (single-phase waveform output mode)
7
6
(1)
, P8
, P8
pins in group 1 are counted (See Figure 21.20)
NOTES:
i = 0 to 3
BCK1 to BCK0, IT : Bits in the GiBCR0 register
RST2 to RST0 : Bits in the GiBCR1 register
1. Divider is reset when both BTiS bit and BTS bit are set to "0".
1
0
Base timer reset
2
f
BTi
"
The timer increments
counter on all edge
b0 to b13
Base timer
Function
Specification
b14 b15
6
and P7
0
1
The timer decrements
counter on all deges
Overflow signal
IT
7
21. Intelligent I/O (Base Timer)
pins in group 0, and P8
(See the BTiR bit in Figure 10.14)
Base timer
interrupt request
2
".
0