m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 107

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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Table 8.7 Interrupts to Exit Wait Mode
2
0
8.5.3 Stop Mode
1
C
9
_______
NMI Interrupt
Serial I/O Interrupt
Key Input Interrupt
A/D Conversion Interrupt Available in single or single-sweep mode Do not use
Timer A Interrupt
Timer B Interrupt
______
INT Interrupt
CAN Interrupt
Intelligent I/O Interrupt
3 .
B
8 /
In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as
the CPU and peripheral functions operated by these clocks, also stop. The least power required to
operate the microcomputer is in stop mode. The internal RAM holds its data if the voltage applied to the
Vcc pin is 2.5V or more.
Interrupts used to exit stop mode are NMI interrupt, key input interrupt, and INT interrupt.
0
1
8.5.3.1 Entering Stop Mode
3
0
Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The
MCD4 to MCD0 bits in the MCD register become set to "01000
Enter stop mode after setting the followings.
3
J
G
4
• Initial Setting
• Before Entering Stop Mode
a
0 -
o r
n
Set each interrupt priority level after setting the minimum interrupt priority level required to exit stop
or wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit stop mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
(5) Set the PRC0 bit in the PRCR register to "1" (write enabled)
(6) Select the main clock as the CPU clock
Interrupt
• When the CPU clock source is the sub clock,
• When the CPU clock source is the PLL clock,
• When the CPU clock source is the on-chip oscillator clock,
3 .
1
u
Set the CM05 bit in the CM0 register to "0" (main clock oscillates) and CM07 bit in the CM0
register to "0" (clock selected by the CM21 bit divided by MCD register setting)
Set the CM17 bit in the CM1 register to "0" (main clock) and the PLC07 bit in the PLC0 register to
"0" (PLL off)
Set the MCD4 to MCD0 bits to "01000
oscillates), and the CM21 it in the CM2 register to "0" (clock selected by the CM17 bit)
3
, 1
(Interrupt priority level of the interrupt used to exit stop mode > interrupt priority level to exit stop
p
mode
1
(
2
M
0
0
3
6
2
C
interrupt priority level of the interrupts not used to exit stop mode)
8 /
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Available
Available when the internal and external
clocks are used
Available
Available in all modes
Available
Available
Available
M
3
2
C
f o
8 /
4
3
8
) T
8
When CM02=0
______
2
" (divide-by-8 mode), the CM05 bit to "0" (main clock
Available
Available only when the external clock is used
Available
Available in event counter mode or when
the count source is f
Available
Do not use
Do not use
2
" (divide-by-8 mode).
______
When CM02=1
8. Clock Generation Circuit
C32