m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 102

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
8.2 CPU Clock and BCLK
8.3 Peripheral Function Clock
e
E
3
. v
J
Table 8.3 CPU Clock Source and Bit Settings
2
0
The CPU operation clock is referred to as the CPU clock. The CPU clock is also the count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8. In memory expansion or micro-
processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 8.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 8.3 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD register selects the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD register is set to "08
main clock starts running, the CPU clock enters middle-speed mode (divide-by-8).
CPU Clock Source
Main Clock
Sub Clock
On-chip Oscillator Clock
PLL Clock
The peripheral function clock becomes the operation clock or count source for peripheral functions exclud-
ing the watchdog timer.
8.3.1 f
8.3.2 f
1
9
C
3 .
B
f
division when n=0). The CM21 bit determines which clock is selected.
When the CM02 bit is set to "1" (peripheral function stops in wait mode) when entering wait mode, f
f
f
The CNT3 to CNT0 bits in the TCSPR register selects a f
for the intelligent I/O.
The CLK
f
chip oscillator clock. The CM21 bit determines which clock is selected.
When the CM02 bit is set to "1" (peripheral function stop in wait mode) when entering wait mode, f
stops. f
NOTES:
8 /
1
32
1
AD
0
1
, f
, f
3
0
1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock.
3
and f
8
J
8
is the operation clock for the A/D convertor and has the same frequency as the main clock
G
4
, f
a
and f
0 -
n
o r
32
1
AD
3 .
1
u
, f
AD
2n
, 1
3
and f
p
OUT
1
8
2n
2
(
stop running. These clocks also stop in low-power consumption mode.
also stops in low-power consumption mode.
, f
M
0
are used as the operation clock for the serial I/O and the count source for timers A and B.
0
pin outputs f
3
2n
32
6
2
C
are the main clock
and f
8 /
Page 79
, 3
M
2n
3
2
8
C
f o
and f
8 /
4
3
CM0 Register
8
) T
8
32
(1)
CM07
. Refer to 8.4 Clock Output Function for details.
0
1
0
0
or on-chip oscillator clock divided-by-1, -8, -32 ,or -2n (n=1 to 15. No
CM2 Register
2n
division. f
CM21
16
0
0
1
0
" (divide-by-8 mode). Therefore, when the
1
is also used as the operation clock
8. Clock Generation Circuit
CM1 Register
CM17
0
0
0
1
(1)
and on-
1
, f
AD
8
,