m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 231

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)
0
2
16.4.2 Clock Phase Setting Function
1
9
C
3 .
B
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
8 /
0
1
16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
0
3
3
Figure 16.24 shows transmit and receive timing.
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 16.25 shows the transmit and receive timing.
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high ("H"), the STxDi pin is
placed in a high-impedance state. When the SSi pin becomes low ("L"), the first data is output. The
serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and
receive timing.
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4
a
0 -
n
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3 .
Input Signal to the
SS Pin in the Master
Data Output Timing
Data Input Timing
1
Clock Output
(CKPOL=0, CKPH=0)
Clock Output
(CKPOL=1, CKPH=0)
Clock Output
(CKPOL=0, CKPH=1)
Clock Output
(CKPOL=1, CKPH=1)
u
, 1
3
p
1
2
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M
0
0
3
6
2
C
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8 /
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M
3
2
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"L"
"H"
f o
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
8 /
4
8
3
8
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D
0
D
1
_____
D
_____
2
_____
D
3
_____
D
4
D
5
16. Serial I/O (Special Function)
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6
D
7