m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 105

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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8.5.2 Wait Mode
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In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock,
also stop. Because the main clock, sub clock and on-chip oscillator clock continue running, peripheral
functions using these clocks also continue operating.
0
1
8.5.2.1 Peripheral Function Clock Stop Function
8.5.2.2 Entering Wait Mode
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0
If the CM02 bit is set to "1" (peripheral function clock stops in wait mode), f
wait mode. Power consumption can be reduced because the peripheral function that has f
or f
Follow the procedure below to enter wait mode.
Set the interrupt priority level required to exit wait mode to "7" immediately after exiting wait mode.
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J
G
4
• Initial Setting
• Before Entering Wait Mode
• After Exiting Wait Mode
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Set each interrupt priority level after setting the exit priority level required to exit wait mode, con-
trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit wait mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0"
(4) Set the IPL in the FLG register. Then set the exit priority level to the same level as IPL
(5) Set the PRC0 bit in the PRCR register to "1" (write enable)
(6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock),
(7) Set the I flag to "1"
(8) Execute the WAIT instruction
AD
3 .
1
u
3
, 1
p
(Interrupt priority level of the interrupt used to exit wait mode > exit priority level
priority level of the interrupts not used to exit wait mode)
the PLC07 bit in the PLC0 register to "0" (PLL off), and the PLV00 bit in the PLV register to
"0"(cut off power to PLL)
as a count source stops. f
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4
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8
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8
C32
does not stop running.
1
, f
8. Clock Generation Circuit
8
, f
32
, f
2n
and f
interrupt
1
, f
AD
8
, f
stop in
32
, f
2n
,