m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 134

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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11. Watchdog Timer
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Figure 11.1 Watchdog Timer Block Diagram
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The watchdog timer detects a program which is out of control. The watchdog timer contains a 15-bit counter
which is decremented by the CPU clock that the prescaler divides. The CM06 bit in the CM0 register
determines whether the watchdog timer interrupt request or reset is generated when the watchdog timer
underflows. The CM06 bit can be set to "1" (reset) only. Once the CM06 bit is set to "1", it cannot be
changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset.
When the main clock, on-chip oscillator clock, or the PLL clock runs as the CPU clock, the WDC7 bit in the
WDC register determines whether the prescaler divides by 16 or by 128. When the sub clock runs as the
CPU clock, the prescaler divides by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calcu-
lated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock:
When the sub clock is selected as the CPU clock,
For example, if the CPU clock frequency is 30MHz and the prescaler divides by 16, watchdog timer cycle is
approximately 17.5 ms.
The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is
generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler
stop after reset. They begin counting when the WDTS register is set.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting
from the value held when the mode or state is exited.
Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the
watchdog timer.
1
C
9
3 .
B
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1
3
0
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HOLD Signal
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Internal Reset Signal
Write to WDTS Register
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CPU Clock
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CM06, CM07 : Bits in CM0 register
WDC7 : Bit in WDC register
Watchdog timer cycle =
Watchdog timer cycle =
3 .
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1
2
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0
0
3
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Divided by 2 prescaler x counter value of watchdog timer (32768)
Divide by 16 or 128 prescaler x counter value of watchdog timer (32768)
Prescaler
1/128
1/16
1/2
CM07 = 0
WDC7 = 0
CM07 = 0
WDC7 = 1
CM07 = 1
CPU clock
CPU clock
Watchdog Timer
Set to
7FFF
16
CM06
0
1
11. Watchdog Timer
Watchdog Timer
Interrupt Request
Reset