m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 326

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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Table 21.28 HDLC Processing Mode Specifications
0
Transfer Clock
21.4.3 HDLC Data Processing Mode (Group 0 and 1)
Input Data Format
Output Data Format
I/O Method
Bit Stuffing
Flag Detection
Abort Detection
CRC
1
C
9
3 .
B
In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are
available for HDLC control. The channel 0 and 1 are used to generate the transfer clock. No pins are
used.
To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion
result is restored after data conversion. If any data are in the GiTO register after data conversion, the
conversion is terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless
of there being no data in the transmit output buffer. A CRC value is calculated every time one bit is
converted. If no data is in the GiRI register, received data conversion is terminated.
Table 21.28 list specifications of the HDLC data processing mode. Table 21.29 lists registers to be used
and their settings.
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0
1
3
0
3
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3 .
1
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, 1
3
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Item
1
2
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0
0
3
6
2
C
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Page 303
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8-bit data fixed, bit alignment is optional
8-bit data fixed
When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :
• While transmitting,
• While receiving,
While receiving, "0" following five consecutive "1" is deleted.
interrupt (the SRTiR bit in the IIO4IR register)
Write the masked data "01
The CRC1 to CRC0 bits are set to "11
The CRCV bit is set to "1" (set to "FFFF
• While transmitting, CRC calculation result is stored into the GiTCRC register.
• While receiving, CRC calculation result is stored into the GiRCRC register.
When the RSHTE bit in the GiERC register is set to "1" (reception shift operation
While transmitting, "0" following five consecutive "1" is inserted.
Write the flag data "7E
C
The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"
The CRC calculation result is reset by comparing the flag data "7E
The TCRCE bit in the GiETC register is set to "1" (transmit CRC used).
The RCRCE bit in the GiERC register is set to "1" (receive CRC used).
f o
(transmit disabled)
the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis-
ter is set to "1" (CRC reset)
enabled), the transfer clock is generated in the receiver
• The GiPO0 register determines bit rate.
channel 1 waveform generation function.
n : setting value of the GiPO0 register 0000
value set in the GiTB register is converted in HDLC data processing mode and
transferred to the GiTO register
value set in the GiRI register is converted in HDLC data processing mode and
transferred to the GiRB register. The value in the GiRI register is also transferred to
the GiDR register (received data register).
8 /
The transfer clock is generated in phase-delayed waveform output mode of the
4
3
8
) T
8
(1)
.
16
" to the GiCMP3 register to use the special communication
16
21. Intelligent I/O (Group 0, 1 Communication Function)
" to the GiMSKk(k=0, 1) register
(2)
Specification
2
" (X
16
")
16
+X
16
12
to FFFF
+X
5
+1)
16
16
" and matching
n+2
f
BTi